1. Field of the Invention
The present invention relates to memory devices and, in particular, to precharging the column output lines of a memory cell array before reading a word of the array.
2. Description of the Related Art
Computer memory cells are in wide use today. A memory cell stores a bit of data, i.e. a logic-0 or logic-1, sometimes referred to as low or high, respectively, corresponding to the low voltage state (typically V.sub.SS, e.g. ground=0V)) or the high voltage state (typically V.sub.DD, e.g. 3V). New data (i.e., a bit) may be written into the cell, and stored data (i.e., a bit) may be read from the cell. The data stored in a cell is typically read from the cell via an output terminal of the memory cell.
An array of memory cells are typically provided in a memory array architecture, divided into rows and columns. The memory cell array typically provides storage of larger, multi-bit units of data such as bytes or words. Each row of the array usually contains at least one, and typically several, words. Each column of the array typically contains a single column output line which is coupled to every output terminal of the memory cells in that column.
Memory arrays can be implemented in various forms, including Flash EEPROM, DRAM, ROM, and SRAM. Memory arrays are increasingly used in circuits (ICs) in devices such as cellular telephones, answering machines, cordless phones, and other applications. Memory used in ICs in such applications is sometimes referred to as embedded memory.
For some types of memory cells, such as Flash EEPROM, a read operation consists of a pre-period followed by an evaluation period. During the precharge period, all the column output lines of the memory cell array are precharged (initialized), prior to reading the data of the selected word or row, to a certain precharge value (e.g., 1V). During the evaluation period, which follows the precharging, sensing circuitry (e.g. sense amps) can determine the state of an enabled memory cell by detecting whether or not the precharged column output line for that cell discharges or not.
Referring now to FIG. 1, there is shown a circuit diagram illustrating a common-source configured memory array 100. Memory array 100 is a Flash EEPROM memory cell array, although other types of memory cell arrays are also utilized. Each row of array 100 comprises X+1 words, and array 100 comprises Y+1 rows, for a total of (X+1)(Y+1) words. Each word is illustrated for simplicity as having only two memory cells, although in practice each word would contain a larger number of cells (bits), such as 32 or 128, and in any event typically a power of two. Typical values are (Y+1)=512 and (X+1)=16, with 32-bit words, for an 8 k 32-bit word memory.
Designs such as array 100 often provide more than one word per row for practical reasons. For example, if there is only one word per row, the array may be very tall and skinny; however, a more square shape may be desirable for layout purposes. In addition, the taller and skinner an array is, for a given word-size array, the more rows there are and thus the more loading there is on each column output line. Thus, many memory cell architectures provide more than one word per row, where "word" refers to the unit of bits that is either written or read simultaneously.
Whenever a given word is to be read, in the precharge period, all the column output lines (denoted by BIT0, BIT1, of each word) are precharged via the PRECHARGE line to high (V.sub.DD). All the column output lines are precharged since it is not known until the evaluation period (after the address of the word to be read has been provided and decoded) which particular word of which particular row is going to be read. It is only known at this point that some word is going to be read; thus, all column output lines are precharged.
Just before the system or memory clock transitions from high to low to begin the evaluation period, the address of the word is provided to memory control (or decoding) logic, which decodes from the address the row which should be enabled, as well as the particular word of the row that is to be read. This latter determination, in the design illustrated in FIG. 1, determines which of the SA EN (sense amp enable) signals is activated. During the evaluation period, cells of a row are enabled by the row select signal coupled to the gates of the cells switching to high. An enabled cell having its source terminal coupled to ground and its drain terminal coupled to a precharged column output line will conduct if the cell has been erased (stores a logic-0 or low), thereby discharging the column output line via the ground connected common source. Thus, during the evaluation period, a given cell is coupled to the column output line for its column position, and the cell either discharges (to logic-0 (V.sub.SS)) or does not discharge, depending on whether the cell is low (logic-0) or high (logic-1), respectively.
When a column output line is discharged (when the cell has a logic-0 stored), external circuitry, such as a sense amp coupled to the column output lines, can detect the bit stored in the cell if the sense amp is enabled by the appropriate SA EN signal, by detecting whether or not the column output line to which its input is connected has been discharged or not. The sense amp provides an appropriate-format logic-0 or logic-1 signal at a data output terminal or line in accordance with whether or not the discharge is detected.
Thus, for example, if the first word (word 0) of the first row (row 0) is to be read, the address designating this word, and provided by an external source such as a processor, is received by memory control logic some time before the evaluation period begins (typically just before the evaluation period begins, i.e. at the end of the precharge period). The memory control logic in this example generates a ROW 0 SELECT signal and a SA 0 EN signal, which are applied to the memory cell array 100 throughout the entire evaluation period.
When the clock transitions to low and the evaluation period begins, the ROW 0 SELECT signal provided by the memory control logic causes all memory cells of all X+1 words of row 0 to be enabled, and the SA 0 EN signal enables only the sense amps coupled to the column output lines for word 0. All of the source terminals of all memory cells are coupled to the common source line, which is grounded to V.sub.SS. Thus, any of the memory cells of row 0, from any of words 0 through X+1, which have a logic-0 stored therein, cause the respective column output line to which the cell's drain (output) terminal is coupled to be discharged to zero through the common source ground connection. However, this discharge or lack of discharge is detected only by the enabled sense amps, i.e. those for word 0. The other sense amps are disabled and ignore any discharge or lack thereof for the other column lines. During the evaluation period, therefore, all of the cells on the selected row which are erased (store logic-0) will discharge their columns, regardless of whether they are associated with the word being read. During the next precharge period, all of the discharged columns have to be recharged again, resulting in a power component that is dependent on the number of cells per row being accessed which are erased.
Thus, because all the column lines of the array are precharged, and because all the memory cells of a given row are enabled and are coupled to a common source line, power is wasted when columns have be re recharged again in subsequent read cycles, because the columns were unnecessarily discharged in the previous read cycle. (In general, if a proper subset of the memory cells of a row are being read, the other memory cells of the row which are not being read can be needlessly precharged and discharged, thus causing power waste.) For example, if word 0 of row 0 is to be read, and bit 0 of word 1 has a zero stored therein, then its associated column output line is first precharged, then discharged, and then must be precharged again for subsequent read operations. This results in a waste of power which can be particularly problematic in battery powered devices such as cellular phones or cordless phones. The worst case is a read operation following an erase of the entire memory array. In this case, every cell of X words of the X+1 words of the enabled row are needlessly discharged, and have to be precharged again before another read. Thus, memory cell arrays which have more than one word per row (or which provide for reads of less than all memory cells of the row), which utilize read operation column output line precharging, and which have a common source line, can inefficiently utilize power in unnecessarily precharging and discharging column output lines of words not being read.